TRIANGLE FRAME: I2C Interface or TWI (Two Wire Interface)

In embedded systems a simple function rarely exists alone. A simple pushbutton and LEDs controller is useful but if that controller cannot report when a user has pressed a button or share the status its LED indicate, the controllers is not worth it.

Many embedded systems include peripheral devices connected to the microprocessor in order to expand its capabilities..

I2C Bus Tutorial

For example Ad fruit Motor Shield SPI, L3G4200D 3-Axis Gyro I2C or SPI, 1.44"LCD Display USART etc. Data transmission between two these entities plays a major role in designing embedded systems. In general the medium of data transmission can be either serial or parallel. All these peripheral devices interface with the microcontroller via a serial protocol. Protocol is a language that defines the mode of communication between systems and devices like protocols specify the aspects of inter-device communications including bit ordering, bit pattern meanings, electrical and mechanical aspect. UART, SPI, TWI or USB are some of the protocols widely used in embedded systems for serial data communication. The key to increase the value is communication on a communication bus of choice for embedded systems of all sizes.

1. UART (Universal Asynchronous Receiver and transmitter):

The first chip on UART was designed in around 1971. It is one of the simplest forms of data transmission from a controller/PC. It requires a minimum of two pins (transmitter and receiver pin) and a common ground line for data communication. The UART chip is generally found inbuilt in most of the microcontrollers.In order to communicate the controller with PC a level converter IC like MAX232/233 is needed. Moreover to establish synchronization between two entities, both the devices must transmit or receive the data at same baud rate (the baud rate must be previously known at both the ends). Because of its speed limitation, UART is not used for high speed devices. For more details about UART interfacing refer ATmega16 USART.

2. SPI (Serial Peripheral Interface):

SPI was developed by MOTOROLA and it is very renowned name in data transmission. It has only three lines (i.e. MISO, MOSI and SCK) for data transmission as well as for handshake unlike UART (which requires 9 pins for full feature operations). In SPI communication there is only one MASTER controller and one SLAVE controller, and hence the slave addressing is not required. It is a full duplex serial data communication process.

The MASTER can read from MISO line while transmitting data on MOSI line. The MASTER controls the complete process of data transmission and also provides synchronization clock on the SCL line. Since the synchronization is done by the MASTER itself, the SLAVE device need not worry about the clock frequency at other end. The data size is not restricted to 8-bit data.

The main disadvantage in SPI interfacing is that it can be established only for short distance communication unlike USART. Though only three pins are required for data transmission, one additional pin (SS) is required in SLAVE device. The number of pin required for communication is more as compared to TWI (explained later). For more details refer to SPI INTERFACING AVR.

3. USB (Universal Serial BUS):

The protocol was developed and invented by Intel. The development started in 1994 and in 2008 it became the most popular name in the field of data transmission replacing most of the serial and parallel devices. The main advantage of USB is its speed. The speed of data transmission in USB devices is very high. Many of the microcontrollers (like AT89C51/S51/ S52, ATmega16/8, etc.) don’t support USB communication. There is a wide range of controllers available in AVR too which support the USB communication.

4. TWI (Two wire interface):

The TWI / I²C (I-two-C) protocol was invented by Philips. In TWI the serial data transmission is done in asynchronous mode. This protocol uses only two wires for communicating between two or more ICs. The two bidirectional open drain lines named SDA (Serial Data) and SCL (Serial Clock) with pull up resistors are used for data transfer between devices.

One of the two devices, which controls the whole process, is known as Master and the other which responds to the queries of master is known as Slave device. The ACK (acknowledgement) signal is sent/received from both the sides after every transfer and hence reduces the error. SCL is the clock line bus used for synchronization and is controlled by the master. SDA is known as the data transfer bus.

I²C/TWI is a half duplex serial transmission and hence the data flow can be in a direction at a time. The data transfer rate depends on crystal frequency of slave controller. The rate of data transfer refers to clock frequency on SCL bus which must be 1/16^th of slave frequency.

The TWI or I²C is one of the serial data transfer protocols used in embedded systems. It was created by NXP Semiconductors, originally a Phillips semiconductor division, to attach slow speed peripheral devices to the embedded microprocessor. It is used for low to medium data rate communication. EPROM, real time clock system storage devices, remote temperature sensors and I/O port expanders are some examples of slow peripheral devices. In TWI the serial data transmission is done in asynchronous mode. This protocol uses only two wires for communicating between two or more ICs. I2C is a Multi-point protocol in which a maximum up-to 128 peripheral devices can be connected to communicate along the serial interface which is composed of a bi-directional line (SDA) and a bi-directional serial clock (SCL). The two bidirectional open drain lines named SDA (Serial Data) and SCL (Serial Clock) with pull up resistors. The bus consists of just two wires or circuit traces, one for clock and the other for data, with a pull-up resistor on each wire of the bus. One of the two devices, which control the whole process, is known as Master and the other which responds to the queries of master is known as Slave device. The ACK (acknowledgement) signal is sent/received from both the sides after every transfer and hence reduces the error. SCL is the clock line bus used for synchronization and is controlled by the master. SDA is known as the data transfer bus. Figure below shows a typical arrangement of I2C.

Once we have understood the basics of TWI let’s get in depth about each part of I2C arrangement and functions.

1.Working of TWI

Both TWI lines SDA and SDC are bi-directional therefore outputs connected to the TWI are open collector type so each line is connected to a voltage supply via Pull up resistor. Pulling the lines to the ground is considered a logical zero while letting it float is considered as logical ‘1’. When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high. Releasing SDA to float high again would be a stop marker, signaling the end of a bus transaction.

The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have unique address. The TWI bus is a multi-master bus where one or more devices, capable of taking control of the bus, can be connected. The master supplies the clock; it initiates and terminates transactions and the intended slave (based upon the address provided by the master) acknowledges the master by driving or releasing the bus. The slave cannot terminate the transaction but can indicate a desire to stop or terminate by a “NAK” or not-acknowledge. Addressing opens the lines of communication between the master and its intended slave device and the master keeps the connection open until it wishes to terminate the connection (when the master is finished with the slave).

The mode of operation whether a device will act as a master or as a slave is distinguished by the TWI status codes in the TWI Status Register (TWSR) and by the use of certain bits in the TWI Control Register (TWCR). The status codes are divided in Master and Slave codes and further in receive and transmit related codes. Status codes for Bus Error and Idle also exist. The status codes are divided into four groups: Master Transmitter Mode (MT), Master Receiver Mode (MR), Slave Transmitter Mode (ST) and Slave Receiver Mode (SR).

Once decided which device will act as master the data transmission takes place. Only Master devices can drive both the SCL and SDA lines while a Slave device is only allowed to issue data on the SDA line. Data transfer is always initiated by a Bus Master device.

A high to low transition on the SDA line while SCL is high is defined to be a START condition or a repeated start condition.

A START condition is always followed by the (unique) 7-bit slave addresses and then by a Data Direction bit. The Slave device addressed now acknowledges to the Master by holding SDA low for one clock cycle. If the Master does not receive any acknowledgement the transfer is terminated. Depending of the Data Direction bit, the Master or Slave now transmits 8-bit of data on the SDA line. The receiving device then acknowledges the data. Multiple bytes can be transferred in one direction before a repeated START or a STOP condition is issued by the Master. The transfer is terminated when the Master issues a STOP condition. A STOP condition is defined by a low to high transition on the SDA line while the SCL is high. If a Slave device cannot handle incoming data until it has performed some other function, it can hold SCL low to force the Master into a wait-state. All data packets transmitted on the TWI bus are 9 bits long, consisting of one data byte and an acknowledge bit. The master or the control unit includes the clock, Data/Address Register, a START and STOP controller and arbitration detection while the receiver is responsible for acknowledging the reception. The Address Match unit is only used in slave mode, and checks if the received address bytes match the 7-bit address in the TWI Address Register (TWAR). Upon an address match, the Control Unit is informed, allowing correct action to be taken. An Acknowledge (ACK) is signaled by the receiver pulling the SDA line low during the SCL cycle. If the receiver leaves the SDA line high, a NACK is signaled. During data transfer the two wire data register contains the address or data bytes to be transmitted or received. In addition it also contains a register containing the ACK/NON-ACK bit to be transmitted or received.

The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a Master. If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process by synchronizing with Address match unit. Arbitration is a technique which allows to ensure that no two microcontrollers tries to send data at the same time. If the TWI has lost arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated.

As the TWI bus is a multi master bus, it’s possible that two devices initiate a transfer at the exact same time. Arbitration is carried out through the next stages of the transaction, and the first device attempting to transmit a logical ‘1’ while another device transmits ‘0’ will lose arbitration. This can due to the physical characteristics of the bus easily be detected. If one device pulls a line low, the others cannot transmit high. When a device has lost arbitration, it must stop transmitting and wait until the next STOP condition before trying to take control of the bus again.

TIMING DIAGRAM

Data transfer is initiated with the START bit (S) when SDA is pulled low while SCL stays high. Then, SDA sets the transferred bit while SCL is low (blue) and the data is sampled (received) when SCL rises (green). When the transfer is complete, a STOP bit (P) is sent by releasing the data line to allow it to be pulled up while SCL is constantly high. In order to avoid false marker detection, the level on SDA is changed on the negative edge and is captured on the positive edge of SCL.

TWI (Two Wire Interface) Details:

TWI (Two wire interface) as the name suggests is based on two wires namely SDA (Serial Data) and SCL (Serial Clock). The master controls the two buses and slave always responds to the master’s queries. There can be multi master or single master mode of communication. The article Using I2C in AVR ATmega32shows the communication between two ATmega32 controllers single master mode.

The master initiates the communication by sending a Start condition on the SDA and SCL line. A high to low transmission on SDA line while SCL is high is defined as a Start condition.

In return the master updates its status values. The status values are the predefined values and cover the different states that the TWI can be in after every operation of data transfer. Error detection or the faulty transmission can be detected by looking at the status values. The status values are determined by using TWSR register for AVR microcontroller (refer ATmega32 TWI registers).

The start condition is followed by seven bit slave address and then by a data direction bits. Every slave is recognized by its address (The slave address is assigned to slave device at the time of slave initialization). The Data Direction Bit tells the direction of data flow. If the data direction bit is logic zero the master performs write operation with slave or if the data direction bit is logic one then the master performs read operation from slave. The data direction bit is also known as Read/Write Control bit.

If a particular slave device is addressed, the slave acknowledges to master by holding SDA low for one clock cycle.

Depending on the DDB (data direction bit) the master or slave transmits the data (8-bit data) on SDA pin. Receiving device then acknowledges the data. The acknowledgement signal updates the status register.

When data transmission is completed the Stop Condition is issued by master to stop the communication. A low to high transmission on SDA line while SCL is high is defined as a Stop condition.